Title:
【発明の名称】III―V/II―VI半導体インターフェイス製造法
Document Type and Number:
Japanese Patent JP2000501889
Kind Code:
A
Abstract:
A method for repeatably fabricating GaAs/ZnSe and other III-V/II-VI semiconductor interfaces with relatively low stacking fault densities in II-VI semiconductor devices such as laser diodes. The method includes providing a molecular beam epitaxy (MBE) system including at least a group III element source, a group II element source, a group V element source and a group VI element source. A semiconductor substrate having a III-V semiconductor surface on which the interface is to be fabricated is positioned within the MBE system. The substrate is then heated to a temperature suitable for III-V semiconductor growth, and a crystalline III-V semiconductor buffer layer grown on the III-V surface of the substrate. The temperature of the semiconductor substrate is then adjusted to a temperature suitable for II-VI semiconductor growth, and a crystalline II-VI semiconductor buffer layer grown on the III-V buffer layer by alternating beam epitaxy. The group II and group VI sources are operated to expose the III-V buffer layer to a group II element flux before exposing the III-V buffer layer to a group VI element flux.
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Inventors:
Depuit, James M.
Guha, Splatic
Herse, Michael A.
Low, rich
Miller, Thomas Jay.
C, Borgen
Gayness, James M.
Guha, Splatic
Herse, Michael A.
Low, rich
Miller, Thomas Jay.
C, Borgen
Gayness, James M.
Application Number:
JP52209297A
Publication Date:
February 15, 2000
Filing Date:
December 05, 1996
Export Citation:
Assignee:
Minnesota Mining and Manufacturing Company
Philip Electronics Namrose Fennaught Shap
Philip Electronics Namrose Fennaught Shap
International Classes:
H01L21/363; H01L21/443; H01L33/00; H01S5/00; H01S5/347; (IPC1-7): H01S5/347; H01L21/363; H01L33/00
Attorney, Agent or Firm:
Takashi Ishida (4 others)