Title:
【発明の名称】結合された論理ゲートおよびラッチ
Document Type and Number:
Japanese Patent JP2000516778
Kind Code:
A
Abstract:
A circuit combines the functions of a logic gate and a latch to lower steady state power dissipation during gate operation. The circuit operates in two modes: a flow-through mode and a latched mode. In the flow-through mode, a gate portion which receives one or more digital input signals implements the complement of a desired Boolean logic function on the input signals and provides an internal signal. The gate portion may have a steady-state power dissipation while providing the internal signal. An inverter in a latch portion of the circuit inverts the internal signal to generate an output signal which represents the desired logical combination of the input signals. The inverter provides the output signal with a full-range CMOS voltage. In latched mode, the gate portion is disabled to stop the steady-state power dissipation while the latch portion of the circuit preserves the desired output signal.
Inventors:
Assato, Clayton
Application Number:
JP50811698A
Publication Date:
December 12, 2000
Filing Date:
August 05, 1997
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K3/037; H03K3/356; H03K19/0944; (IPC1-7): H03K3/037; H03K19/0944
Attorney, Agent or Firm:
Takashi Ishida (4 others)