Title:
【発明の名称】送信ラインのインピーダンスマッチング
Document Type and Number:
Japanese Patent JP2001510290
Kind Code:
A
Abstract:
The invention relates to a circuit arrangement for forming an impedance match of transmission lines. The circuit arrangement includes a control state (11), a dynamic input impedance formed by resistances and a transformer (13) provided with primary and secondary coils. The control stage (11) and the input impedance are connected to the poles of the transformer's (13) secondary coil, and transmission lines having mutually different characteristic impedances are connected one at a time to the poles of the transformer's (13) primary coil. According to the invention, the circuit arrangement is characterised in that for forming a resistive input impedance the circuit arrangement includes a processor (15) and means (14) for implementing the match.
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Inventors:
Plated Linen Ori Pekka
Peekare Youni
Pasanen Timo
Peekare Youni
Pasanen Timo
Application Number:
JP2000502577A
Publication Date:
July 31, 2001
Filing Date:
July 09, 1998
Export Citation:
Assignee:
Nokia Networks Osuke Yukichia
International Classes:
H01R29/00; H03H7/38; H03H7/40; H03H11/40; H04B1/04; H04L25/02; (IPC1-7): H03H7/40; H03H7/38; H03H11/40; H04B1/04
Attorney, Agent or Firm:
Minoru Nakamura (9 outside)