Title:
【発明の名称】低雑音集積増幅回路の製造方法
Document Type and Number:
Japanese Patent JP2003504905
Kind Code:
A
Abstract:
A method for configuring low-noise integrated amplifier circuits having an input stage with a transistor includes noise matching the circuit to the real part of a predetermined output impedance of a transfer element connected upstream of the circuit by a choice of process parameters during the production of the circuit and/or of geometry parameters of the integrated components and/or dimensioning the component values of the circuit, the noise figure of the circuit, dependent on a real generator resistance, is less than a predetermined figure in a range wherein the value of the output impedance real part also lies. The required power matching of the input impedance of the circuit to the output impedance is performed by choosing the effective load on a transistor collector to produce a complex voltage gain that, due to the Miller effect, generates an input impedance equal to the complex conjugate of the predetermined output impedance.
Inventors:
Katara, Stefan
Application Number:
JP2001508585A
Publication Date:
February 04, 2003
Filing Date:
May 30, 2000
Export Citation:
Assignee:
Infineon Technologies Actien Gezel Shaft
International Classes:
H03F1/26; (IPC1-7): H03F1/26
Attorney, Agent or Firm:
Kenzo Hara (3 outside)