Title:
読出及び書込動作でバースト順序が異なるアドレッシングを行うメモリデバイス
Document Type and Number:
Japanese Patent JP2004536417
Kind Code:
A
Abstract:
An apparatus enables the reordering of a block of n-bit words output from a plurality of memory cells according to information in certain address bits before outputting at least one n-bit word from a memory device while ignoring those certain address bits before inputting at least one n-bit word into the plurality of memory cells. The apparatus may additionally comprise examining at least two of the least significant bits of a column address and wherein the reordering is responsive to the examining. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA 0 -CA 2 identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA 0 -CA 2 being "don't care" bits assumed to be 000.
Inventors:
Jansen, Jeffrey W.
Application Number:
JP2003512981A
Publication Date:
December 02, 2004
Filing Date:
July 10, 2002
Export Citation:
Assignee:
MICRON TECHNOLOGY,INC.
International Classes:
G11C11/407; G11C7/10; G11C8/00; G11C8/04; G11C11/401; (IPC1-7): G11C11/407; G11C11/401
Attorney, Agent or Firm:
Toshiyuki Maruyama
Takao Miyano
Koichi Kitazumi
Toshiya Nagatsuka
Takao Miyano
Koichi Kitazumi
Toshiya Nagatsuka