Title:
半導体基板内に狭いトレンチを形成する方法
Document Type and Number:
Japanese Patent JP2005516381
Kind Code:
A
Abstract:
A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
Inventors:
Fushiev, Fu-Iouan
Saw, coon, chong
Amato, John, Yi.
Pratt, Bryan, Dee.
Saw, coon, chong
Amato, John, Yi.
Pratt, Bryan, Dee.
Application Number:
JP2003546391A
Publication Date:
June 02, 2005
Filing Date:
November 20, 2002
Export Citation:
Assignee:
General Semiconductor, Inc.
International Classes:
H01L21/28; H01L21/3065; H01L21/308; H01L21/336; H01L21/8234; H01L27/088; H01L29/12; H01L29/423; H01L29/49; H01L29/78; (IPC1-7): H01L29/78; H01L21/28; H01L21/3065; H01L21/336; H01L21/8234; H01L27/088; H01L29/423; H01L29/49
Domestic Patent References:
| JPH0645431A | 1994-02-18 | |||
| JP2001274396A | 2001-10-05 | |||
| JPH09172064A | 1997-06-30 |
Attorney, Agent or Firm:
Akira Koike
Eiichi Tamura
Seiji Iga
Eiichi Tamura
Seiji Iga