Title:
フィードバック乱数発生方法及びシステム
Document Type and Number:
Japanese Patent JP2005538445
Kind Code:
A
Abstract:
A physical random number generator operates to generate a true random bit sequence while a linear feedback shift register and a clock collectively operate to provide a plurality of feedback random bit sequences. In operation, the linear feedback shift register periodically latches the feedback random bit sequences in response to a clock signal having a predetermined operating frequency from the clock. In latching the feedback random bit sequences, the linear feedback shift register includes a plurality of bi-stable latches for linearly shifting a mixed random bit sequence outputted by an XOR gate, which is combined with the true random bit sequence. A decimator receives a feedback random bit sequence and provides an output random bit sequence that is representative of a selective outputting of the feedback random bit sequence.
Inventors:
Laslow, Haas
Application Number:
JP2004533718A
Publication Date:
December 15, 2005
Filing Date:
August 15, 2003
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
G06F7/58; G09C1/00; H03K3/84; (IPC1-7): G06F7/58; G09C1/00; H03K3/84
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki