Title:
パイプライン化ディジタルプロセッサにおけるハザード検出および管理のための方法および装置
Document Type and Number:
Japanese Patent JP2006517322
Kind Code:
A
Abstract:
Methods and apparatus are provided for use in a digital processor having a pipeline for executing instructions. The method includes monitoring instructions in the pipeline for instructions that write to a resource and instructions that read from the resource; for each instruction that writes to the resource, storing a write instruction type and write instruction tracking data; for each instruction that reads from the resource, determining a read instruction type and generating a latency value based on the write instruction type and the read instruction type; and stalling execution of the instruction that reads from the resource by a number of stall cycles in response to the latency value and the write instruction tracking data.
Inventors:
Tomazine, Thomas, Jay.
Wit, david
Chinakonda, Murari
Hooper, William, H.
Wit, david
Chinakonda, Murari
Hooper, William, H.
Application Number:
JP2006503481A
Publication Date:
July 20, 2006
Filing Date:
February 10, 2004
Export Citation:
Assignee:
Analog Devices, Inc.
International Classes:
G06F9/38; G06F9/30
Attorney, Agent or Firm:
Kiyoji Kuzuwa
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