Title:
二重用途レジスタを識別しているアドレス指定パターンに基づいたデータ投機
Document Type and Number:
Japanese Patent JP2007504575
Kind Code:
A
Abstract:
A system may include a memory file and an execution core. The memory file may include an entry configured to store an addressing pattern and a tag. If an addressing pattern of a memory operation matches the addressing pattern stored in the entry, the memory file may be configured to link a data value identified by the tag to a speculative result of the memory operation. The addressing pattern of the memory operation includes an identifier of a logical register, and the memory file may be configured to predict whether the logical register is being specified as a general purpose register or a stack frame pointer register in order to determine whether the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.
Inventors:
James Kay. Pickett
Benjamin Thomas Thunder
Kevin Michael Lepack
Benjamin Thomas Thunder
Kevin Michael Lepack
Application Number:
JP2006536513A
Publication Date:
March 01, 2007
Filing Date:
January 09, 2004
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
G06F9/38; G06F9/34; G06F9/42; G06F12/00
Foreign References:
| US6065103A | 2000-05-16 | |||
| US6065103A | 2000-05-16 |
Attorney, Agent or Firm:
Masatake Suzuki
Ryota Sano
Yoshito Muramatsu
Ryota Sano
Yoshito Muramatsu