Title:
マルチプルアドレス2チャンネルバス構造
Document Type and Number:
Japanese Patent JP2007519121
Kind Code:
A
Abstract:
A processing system is disclosed with a sending component and a receiving component connected by a multiple address two channel bus. The sending device may broadcast on the first channel of the bus read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data. The sending component may also broadcast the read and write address information multiple address locations at a time. The receiving component may store the write data broadcast on the first channel based on the write address information, retrieve the read data from the receiving component based on the read address information, and broadcasting the retrieved read data on the second channel of the bus.
Inventors:
Hoffman, Richard Gerald
Ganasan, Jaya Prakash Subramaniam
Rowery, Thomas John
Remacruz, Perry Wilman Jr.
Ganasan, Jaya Prakash Subramaniam
Rowery, Thomas John
Remacruz, Perry Wilman Jr.
Application Number:
JP2006551212A
Publication Date:
July 12, 2007
Filing Date:
January 20, 2005
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F13/38; G06F13/42
Domestic Patent References:
| JPS61269750A | 1986-11-29 |
Foreign References:
| GB2341766A | 2000-03-22 |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Katsu Sunagawa
Ryo Hashimoto
Tetsuya Kazama
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Katsu Sunagawa
Ryo Hashimoto
Tetsuya Kazama
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