Title:
データドリブン型アーキテクチャメッシュアレイ中のメモリアクセスデバイス制御
Document Type and Number:
Japanese Patent JP2007524142
Kind Code:
A
Abstract:
A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.
Inventors:
Lippincott, Lewis
Cheer, chin, hong
Cheer, chin, hong
Application Number:
JP2006515367A
Publication Date:
August 23, 2007
Filing Date:
June 18, 2004
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F15/82; G06F9/44; G06F15/00; G06F15/163; G06F15/17; G06F15/173; G06F15/78; G06F15/80
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Osamu Miyazaki
Shinsuke Onuki
Tadashige Ito
Osamu Miyazaki