Title:
ベクトル散乱演算機能及びベクトル収集演算機能を提供する命令及びロジック
Document Type and Number:
Japanese Patent JP2014526757
Kind Code:
A
Abstract:
Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.
Inventors:
Old * Ahmed * Barh, a エルモウ stuffer
ドシ, カシティジ, Ey.
Yount, Charles, an R.
A sire, Sulaiman
ドシ, カシティジ, Ey.
Yount, Charles, an R.
A sire, Sulaiman
Application Number:
JP2014531780A
Publication Date:
October 06, 2014
Filing Date:
September 26, 2011
Export Citation:
Assignee:
Intel corporation
International Classes:
G06F17/16; G06F9/30; G06F9/38
Domestic Patent References:
| JP2011134318A | 2011-07-07 | |||
| JP2011514598A | 2011-05-06 | |||
| JPH036663A | 1991-01-14 | |||
| JPH0954769A | 1997-02-25 |
Attorney, Agent or Firm:
Ryuka international patent business corporation