Title:
SEMICONDUCTOR DEVICE, DISPLAY DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP2018050030
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device and a display device, and a method of manufacturing the semiconductor device and a method of manufacturing the display device, capable of suppressing yield reduction.SOLUTION: A semiconductor device has an insulative substrate, a polycrystalline silicon layer, a first gate insulating layer, a first metal layer, an oxide semiconductor layer, a second gate insulating layer, and a second metal layer, and comprises a first top gate planar type thin-film transistor using the polycrystalline silicon layer as a channel and having a source and drain, and a gate, and a second top gate type thin-film transistor using the oxide semiconductor layer as a channel and having a source and drain, and a gate. The source and drain of the first top gate planar type thin-film transistor and the gate of the second top gate type thin-film transistor consist of the second metal layer. The source or drain of the first top gate planar type thin-film transistor and the gate of the second top gate type thin-film transistor are electrically connected with each other.SELECTED DRAWING: Figure 1
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Inventors:
TAKECHI KAZUE
Application Number:
JP2017127872A
Publication Date:
March 29, 2018
Filing Date:
June 29, 2017
Export Citation:
Assignee:
TIANMA JAPAN LTD
International Classes:
H01L29/786; G09F9/00; G09F9/30; H01L21/336; H01L21/8234; H01L27/06; H01L27/088
Domestic Patent References:
JP2013150313A | 2013-08-01 | |||
JP2013102187A | 2013-05-23 | |||
JP2018117154A | 2018-07-26 | |||
JP2011249674A | 2011-12-08 |
Foreign References:
US20150325602A1 | 2015-11-12 | |||
CN103715196A | 2014-04-09 | |||
US20150055051A1 | 2015-02-26 | |||
CN105408813A | 2016-03-16 | |||
WO2011135908A1 | 2011-11-03 | |||
US20130214279A1 | 2013-08-22 |
Attorney, Agent or Firm:
Hideno Kono