Title:
【発明の名称】論理回路診断方法
Document Type and Number:
Japanese Patent JP2501202
Kind Code:
B2
Abstract:
PURPOSE:To increase a fault detection rate by selecting such a specific pin that a clock is not inputted to an input FF group and activating an output FF group by the clock pin. CONSTITUTION:A logic circuit 1 is divided logically into plural partial circuits 2 for the purpose of diagnosis. One partial circuit 2 consists of a logic block 3 composed of a combination circuit, the input FF group 4 positioned in front of the block 3, the FF group 5 behind it, and a clock line 6 inputted to the FF groups 4 and 5. Further, the FF group 4 is replaced possibly with an input edge pin group and the FF group 5 is also replaced possibly with an output edge pin group. Diagnosis input data is set in the FF group 4 and then a clock is applied to the clock line 6 to set the logic operation result of the block 3 in the output group 5, whose contents are read out finally. This process is repeated at every partial circuit to diagnose the circuit 1. Thus, the fault detection rate is improved.
Inventors:
YAMAGUCHI YOSHIJI
SATO YOSHIO
ISHAMA TAKASHI
SATO YOSHIO
ISHAMA TAKASHI
Application Number:
JP23968786A
Publication Date:
May 29, 1996
Filing Date:
October 08, 1986
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
HITACHI KONPYUUTA ENJINIARINGU KK
HITACHI KONPYUUTA ENJINIARINGU KK
International Classes:
G01R31/28; G01R31/317; H03K19/00; (IPC1-7): G01R31/317
Attorney, Agent or Firm:
Makoto Suzuki