Title:
【発明の名称】シリアル・データ通信装置
Document Type and Number:
Japanese Patent JP2559912
Kind Code:
B2
Abstract:
Described is a synchronizing device that aligns the receiver of a communications device with the bit boundaries of a serially received data stream. The device delays a bit in a synchronized data stream and correlates it with a next bit in said data stream. If there is no change in the bit pattern for a predetermined number of bits or within a set bit time, a signal is generated to reset a synchronization latch. Thereafter, the receiver is synchronized to the incoming data.
Inventors:
MAAKU ARAN JONSON
Application Number:
JP4219291A
Publication Date:
December 04, 1996
Filing Date:
February 15, 1991
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
H04L7/00; H04L7/02; (IPC1-7): H04L7/00
Attorney, Agent or Firm:
Hiroshi Sakaguchi (3 outside)