Title:
【発明の名称】メモリ
Document Type and Number:
Japanese Patent JP2585235
Kind Code:
B2
Abstract:
PURPOSE:To incorporate an error correcting function by storing horizontal and vertical parities of an input data in a memory at the time of the inputting of the data, comparing the parities with those of an output data at the time of outputting, and correcting an error. CONSTITUTION:A data inputted from data input terminals DI1-DI4 are stored in a memory cell array MA1, and at the same time, the parities against the input data generated by a parity generating circuit P1 are stored in a memory cell array MA2. To output data from the data output terminals DI1-DI4 of the array MA1, the parity generated by the parity generating circuit P2 and that stored in the array MA2 are compared with each other by a comparator C and by the result of the comparison, an error data is corrected by a correction circuit DCB, and thus the data are outputted to output terminals DO1-DO4. Accordingly, the error correction can be executed almost without increasing an access time.
Inventors:
NANBU HIROAKI
YAMAGUCHI KUNIHIKO
KANETANI KAZUO
OOHATA KENICHI
YAMAGUCHI KUNIHIKO
KANETANI KAZUO
OOHATA KENICHI
Application Number:
JP26765586A
Publication Date:
February 26, 1997
Filing Date:
November 12, 1986
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
HITACHI DEBAISU ENJINIARINGU KK
HITACHI DEBAISU ENJINIARINGU KK
International Classes:
G11C11/413; G06F12/16; G11C11/34; G11C29/00; G11C29/42; H01L21/8229; H01L27/10; H01L27/102; (IPC1-7): G11C29/00; G06F12/16; G11C11/413
Domestic Patent References:
| JP61182151A | ||||
| JP5891600A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)