Title:
【発明の名称】集積回路試験装置
Document Type and Number:
Japanese Patent JP2645864
Kind Code:
B2
Abstract:
PURPOSE:To generate a fault image at all time even without a quality sample by providing 1st and 2nd memory circuits, a brightness histogram generating circuit, and a histogram equalizing circuit. CONSTITUTION:An observation image of the test device DUT of the 1st memory circuit 6 is inputted to the brightness histogram generating circuit 23 to generate a histogram even as to insulation brightness. Then image data generated from the histogram and a design logic map is inputted to the histogram equalizing circuit 24. Then histograms of both images are compared and matched to find a conversion coefficient for converting the histogram curve of a design raster image so that histogram curves conform with each other. This conversion coefficient is used to adjust the relative brightness of a design raster image for referencing which is obtained from the design logic map and the result is inputted as a design raster image of an absolute value to the 2nd memory circuit 7. Then a difference circuit 8 calculates the difference between the DUT image of the circuit 6 and the raster image obtained from the design logic map of the circuit 7.
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Inventors:
KUJI NORIO
Application Number:
JP21445488A
Publication Date:
August 25, 1997
Filing Date:
August 29, 1988
Export Citation:
Assignee:
NIPPON DENSHIN DENWA KK
International Classes:
G01R31/302; G01R31/28; H01L21/66; (IPC1-7): G01R31/302
Attorney, Agent or Firm:
Kugoro Tamamushi (2 outside)