Title:
【発明の名称】ダイナミック型半導体記憶装置及びその製造方法
Document Type and Number:
Japanese Patent JP2674085
Kind Code:
B2
Abstract:
PURPOSE:To increase a storage capacity per unit area by a method wherein a first electrode is formed making a part of it overlap another first electrode of an adjacent memory cell and a second electrode is formed including the region which is common to a pair of the overlapped first electrodes and sandwiched in between them. CONSTITUTION:A capacitor is provided with a first electrode 7a connected to a MOS transistor and a second electrode 9 which faces toward the electrode 7a. And, the first electrode 7a is formed making a part of it overlap a first electrode 6a of an adjacent memory cell, and a second 9 is formed including the region which is common to a pair of the overlapped first electrodes 7a and 6a and sandwiched in between them. As mentioned above, the storage electrodes 6a, 6b, 7a, and 7b of adjacent memory cells are formed overlapping each other, so that a storage capacity per unit area is increased and moreover the rear part of the storage electrode contributes to a storage capacity to enable a memory of this design to increase further in a storage capacity.
Inventors:
Tadashi Ema
Application Number:
JP12087888A
Publication Date:
November 05, 1997
Filing Date:
May 18, 1988
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP62179759A |
Attorney, Agent or Firm:
Teiichi Ijiba (2 outside)