Title:
【発明の名称】アドレスコントロールメモリ回路
Document Type and Number:
Japanese Patent JP2720773
Kind Code:
B2
Abstract:
PURPOSE:To enable a function tester to freely generate an arbitrary pattern memory address and to generate a long and large pattern in a pseudo-executing way. CONSTITUTION:An address counter 1 starts counting operations from '0' and sends a pattern memory address 11. A comparator 3 compares a branching address value 12 from a branching address memory 2 with the address 11. When the value 12 coincides with the address 11, a branched address value 14 from a branched address memory 4 is loaded into the counter 1 and a pointer counter 5 counts a pointer address 15 and outputs the next pointer address 15. The counter 1 can easily generate an arbitrary address by starting the counting operations from the branched address value 14.
Inventors:
MYOGA TOSHUKI
Application Number:
JP29161893A
Publication Date:
March 04, 1998
Filing Date:
November 22, 1993
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/3183; (IPC1-7): G01R31/3183
Domestic Patent References:
| JP61253480A | ||||
| JP4236375A | ||||
| JP469783U |
Attorney, Agent or Firm:
Yoshiyuki Iwasa