Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP2748400
Kind Code:
B2
Abstract:
An integrated circuit including a plurality of circuits having the same input impedance, arranged at regular intervals, and applied with a signal from a single signal source, is disclosed in which the input impedance is substantially capacitive, the characteristic impedance of a signal line connected to the signal source for sending the signal to the circuits is given by Z0 2ROOT L/C, where L indicates the inductance of the signal line per one circuit, and C indicates the combined capacitance of the parasitic capacitance of the signal line per one circuit and the input capacitance of each circuit, the signal line is terminated by a circuit element having impedance equal to the characteristic impedance Z0, and the signal source has output impedance equal to the characteristic impedance Z0.
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Inventors:
ONO KOICHI
HOTSUTA MASAO
NENE YOSHITO
HOTSUTA MASAO
NENE YOSHITO
Application Number:
JP10463388A
Publication Date:
May 06, 1998
Filing Date:
April 27, 1988
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
H03M1/36; H03K17/16; H03K17/60; H03K19/0175; H03M1/06; (IPC1-7): H03M1/36; H03K19/0175; H03M1/06
Domestic Patent References:
| JP53107248A | ||||
| JP4918235A | ||||
| JP413843B1 | ||||
| JP452847B1 | ||||
| JP5024103Y1 |
Attorney, Agent or Firm:
Masatoshi Isomura