Title:
【発明の名称】自己ルーチングスイッチ回路
Document Type and Number:
Japanese Patent JP2751698
Kind Code:
B2
Abstract:
In an input queuing self-routing switching system, each input buffer generates a reserve bit indicating that a cell of the buffer is a winner of a contention a previous contention cycle. A memory stores sets of path status bits and reads a corresponding set of path status bits for coupling to the input buffers as it receives cell destination addresses and reserve bits therefrom. Each path status bit indicates that a cell of the corresponding buffer is a contention loser if the reserve bit is not received during a subsequent contention cycle, or indicates that the cell is a winner of a contention when the reserve bit is received. Each input buffer is responsive to a contention timing signal for reading the destination address from a cell position identified by a cell pointer, and supplies the retrieved address and the reserve bit to the memory. The cell pointer of each buffer is shifted backwards when the corresponding path status bit indicates that the cell of the buffer is a contention loser and generates the reserve bit when the path status bit indicates that the cell is a contention winner. Each buffer further responds to a transmit timing signal for launching a cell therefrom to a self-routing network when that cell has been indicated as a contention winner by the path status bit.
Inventors:
SUGAWARA TSUGIO
Application Number:
JP33076291A
Publication Date:
May 18, 1998
Filing Date:
December 13, 1991
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H04Q3/52; H04L12/863; H04L12/931; H04Q11/04; (IPC1-7): H04L12/28; H04Q3/52; H04Q11/04
Domestic Patent References:
| JP1258527A | ||||
| JP2142240A |
Attorney, Agent or Firm:
Naotaka Ide