Title:
【発明の名称】コンピュータシステム、アライン制御装置および方法
Document Type and Number:
Japanese Patent JP2792699
Kind Code:
B2
Abstract:
A method and apparatus are disclosed for aligning a plurality of multi-processors (10). The apparatus preferably comprises an alignment unit (20) associated with each processor and a logic network (30) for combining the output of the alignment unit and for broadcasting information to these units. Alignment is achieved by inserting in the instruction stream of each processor that is to be aligned a request for alignment, by testing for prior completion of any instructions that must be completed and by causing all processors to wait until they have all made the request for alignment and completed necessary prior instructions. The alignment unit associated with each processor monitors the instruction stream to detect a request for alignment. When all the units have made such a request, the logic network informs the alignment units; and the alignment units inform the processors.
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Inventors:
HIRISU DABURYUU DANIERU
Application Number:
JP50229289A
Publication Date:
September 03, 1998
Filing Date:
February 01, 1989
Export Citation:
Assignee:
SHINKINGU MASHIINZU CORP
International Classes:
G06F9/46; G06F9/52; G06F9/38; G06F15/16; G06F15/177; G06F15/80; (IPC1-7): G06F15/16; G06F9/38
Other References:
Ｄｒｏｃ．ｏｆ ＡＳＰＬＯＳ▲ＩＩＩ▼ Ｖｏｌ．２４ Ｓｐｅｌｓｓｖｅ １９８９ Ｐ．５４−６３
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)