Title:
【発明の名称】IC試験装置
Document Type and Number:
Japanese Patent JP2810342
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To eliminate the loss time of an IC testing device between tests and, at the same time, to reduce the labor required for generating a program. SOLUTION: The test signals of the A/D 19 and D/A 20 of an IC 18 to be tested are delivered and received by means of modules 14-17. The modules 14-17 output end signals a-d upon completing the delivery and reception of the signals. In order to select the module which outputs an end signal to be detected in each test, module selecting conditions are stored in advance in a memory 4. Whenever the end signals 1-d are outputted, the corresponding F/Fs 9-12 are set. The F/F corresponding to the module which does not output the end signal is preset under the selecting condition. When all F/Fs 9-12 are set, a gate 13 outputs a final end signal (z) indicating the completion of one test. When an SQPG (sequential pattern generator) 1 detects the signal (z), the SQPG 1 reads out the selecting condition of the next test from the memory 4 by outputting a next test address to a register 2 so that the next test can be executed without loss time.
Inventors:
Naoshi Saito
Application Number:
JP32158195A
Publication Date:
October 15, 1998
Filing Date:
December 11, 1995
Export Citation:
Assignee:
Asia Electronics Co., Ltd.
International Classes:
G01R31/28; G01R31/316; H01L21/66; G01R31/26; (IPC1-7): G01R31/316; G01R31/26; G01R31/28
Domestic Patent References:
| JP5203702A |
Attorney, Agent or Firm:
Toru Yui (2 outside)