Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2825401
Kind Code:
B2
Abstract:
A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selector circuit each arranged for k-unit group of said gates, for selecting said gates in unit of k-unit group; a plurality of data transfer paths for transferring data via said gates selected by said gate selector circuit; a first register group composed of a-units of data registers for transferring data simultaneously to and from said data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting said data transfer paths connected to said designated data input/output gates with said data registers so that said data transfer paths connected to said designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (Lxk) under the following conditions: if a (mod k) = 0,1, L = (a/k ) + 1 if other than the above, L = (a/k ) + 2 where L denotes a maximum number of said gate selecting means selectable simultaneously.
Inventors:
TODA HARUKI
Application Number:
JP23058392A
Publication Date:
November 18, 1998
Filing Date:
August 28, 1992
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G11C11/407; G11C7/10; G11C11/401; G11C11/409; (IPC1-7): G11C11/407; G11C11/409
Domestic Patent References:
| JP4132076A | ||||
| JP442490A | ||||
| JP3205689A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)