Title:
【発明の名称】CMOSトランジスター素子の方形型セル
Document Type and Number:
Japanese Patent JP2847132
Kind Code:
B2
Abstract:
The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.
Inventors:
KA AKEMICHI
GO JU
KO KENSHO
GO AKYOSHI
YU DAIRITSU
GO JU
KO KENSHO
GO AKYOSHI
YU DAIRITSU
Application Number:
JP28093695A
Publication Date:
January 13, 1999
Filing Date:
October 27, 1995
Export Citation:
Assignee:
KAHO DENSHI KOFUN JUGENKOSHI
International Classes:
H01L21/8238; H01L27/02; H01L27/092; H01L29/06; H01L29/08; H01L29/10; H01L29/423; (IPC1-7): H01L21/8238; H01L27/092
Domestic Patent References:
| JP6295988A | ||||
| JP5315614A | ||||
| JP778990A |
Attorney, Agent or Firm:
Eiji Saegusa (2 others)