Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP2894900
Kind Code:
B2
Abstract:
PURPOSE:To disable a test circuit to operate after execution of the test even with no impression of voltage on an external terminal. CONSTITUTION:An input buffer circuit 2 for a test circuit is connected with an external terminal 1 via a fuse 3, and a P-type transistor 5 in which both the gate and source are in connection with the power source is connected to the input buffer circuit 2 side of the fuse 3 interposed, and further a depression type transistor 4 is furnished where the input to the input buffer circuit is connected with the ground potential. When the test circuit is no more needed, the fuse 3 is allowed to blow off by impressing a voltage higher than the supply voltage on the external terminal, and thereby the input buffer circuit 2 is separated from the external terminal 1. Thereby the input to the input buffer circuit 2 depends only upon the depression type transistor 4 to eliminate necessity for impressing a voltage on the external terminal at all times.
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Inventors:
ORITA NOBUYUKI
Application Number:
JP22203692A
Publication Date:
May 24, 1999
Filing Date:
July 28, 1992
Export Citation:
Assignee:
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
International Classes:
G01R31/28; H01L21/66; H01L21/822; H01L27/04; H01L27/10; (IPC1-7): G01R31/28; H01L21/66; H01L21/822; H01L27/04; H01L27/10
Domestic Patent References:
| JP5160345A |
Attorney, Agent or Firm:
Seiichi Kuwai