Title:
【発明の名称】時間双方向シミュレーション装置
Document Type and Number:
Japanese Patent JP2924968
Kind Code:
B2
Abstract:
PURPOSE:To not only advance circuit operation with time, but also easily put the operation back to a past state by cascading a counter and a memory by making the register of an object circuit into a model. CONSTITUTION:A converting means 12 converts the contents of the register part 11 of a logic circuit 10 into the contents of a memory 2 and a counter 1 which counts a clock. A control means 6 set an optional time T in the counter, writes the logic of clock time T for setting in the register part 11 of a logic circuit 10 into an address T of the memory 2, and then reads the contents set in the register part 11 out of the address of the memory 2. The simulation signal of a logic simulation part for the logic circuit 10 in the actual object circuit is advanced with time or put back to the past to obtain the contents of the register 11 at optional time. Consequently, the circuit operation is not only advanced with time, but also traced back to the past.
Inventors:
HIROSE FUMYASU
NIITSUMA JUNICHI
NIITSUMA JUNICHI
Application Number:
JP18612589A
Publication Date:
July 26, 1999
Filing Date:
July 20, 1989
Export Citation:
Assignee:
FUJITSU KK
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP6312039A | ||||
| JP59117660A |
Attorney, Agent or Firm:
Yoshiyuki Osuge (1 outside)