Title:
【発明の名称】MOS集積回路への電圧印加回路
Document Type and Number:
Japanese Patent JP2931843
Kind Code:
B2
Abstract:
Circuit for resetting power-on in order to provide for the starting-up of a MOS technology integrated circuit. It comprises a supply terminal (A), an earth (M) and an output (S), a capacitor (C1) connected between the earth (M) and the node (1), the charging of which capacitor is controlled via a p-type transistor (T1) connected between (A) and the node (1), an inverting gate (I1, T7) with modifiable threshold voltage, whose input is connected to the node (1), an invertor (I2) connected between the output of the inverting gate (I1, T7) and the output (S), a current source (T8) connected in series to a divider circuit (D1, D2) controlling the first p-type transistor (T1), and a circuit (C) possessing a transfer function VS = f (VE) of inverting type, the said circuit (C) being connected between the output (4) of the inverting gate and the current source (T8) so as to control the operation of the current source.
Inventors:
BURYUNO DEYUBYUJE
Application Number:
JP23389A
Publication Date:
August 09, 1999
Filing Date:
January 04, 1989
Export Citation:
Assignee:
ESU TEE MIKUROEREKUTORONIKUSU SA
International Classes:
H01L27/04; H01L21/822; H03K3/3565; H03K17/22; H03K17/687; H03K19/00; H03K19/003; (IPC1-7): H03K17/22
Attorney, Agent or Firm:
Takashi Koshiba