Title:
【発明の名称】図面作成支援装置
Document Type and Number:
Japanese Patent JP2966441
Kind Code:
B2
Abstract:
PURPOSE:To reduce interference evading operation by including the adoption of a quadrantal tree model, plotting order determination based upon a prescribed rule, interference check, the setting of interference validity, the expansion of a required drawing area, the uniformity of graphic confusing degree, etc., in a computer. CONSTITUTION:The computer constituted of an arithmetic processor 2 for deciding a drawing position of graphic provided with a data input part 2a, a NOT scale processing part 2b, a plotting commanding part 2c, a result output part 2d, etc., and an interference checking/evading arithmetic processor 4 provided with an optimum arrangement part 4a, a plotting information control part 4b, an interference detecting/ evading part 4c, and an expanded graphic forming part adops the quadrantal tree model, defines a drawing on a plane as a rectangle and determines the plotting order successively from the lowest degree of freedom relating to a plotting position. The interference check of rectangular definition, the setting of a graphic permitting interference and a graphic inhibiting interference, the decision of the confusing area of graphics, the expansion of the graphics in the area, and confusion degree uniformity based upon a NOT scale function are similarly executed to reduce the interference evading operation.
Inventors:
ONO SATORU
YOSHINAGA TOSHIAKI
SUZUKI MASAKI
KAWABATA JUNICHI
YOSHINAGA TOSHIAKI
SUZUKI MASAKI
KAWABATA JUNICHI
Application Number:
JP23567989A
Publication Date:
October 25, 1999
Filing Date:
September 13, 1989
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
F16L1/00; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP63150763A | ||||
| JP63276176A | ||||
| JP6194891U |
Attorney, Agent or Firm:
Sakuta Yasuo