Title:
【発明の名称】改良された試験手段を備える集積回路メモリ
Document Type and Number:
Japanese Patent JP2992555
Kind Code:
B2
Abstract:
An electrically-programmable integrated circuit memory in which the selected memory cell is read by comparing its current output with that of a reference cell, plus a bias current. The bias current is different in test mode than it would be during a normal read operation. The result of this is that, in test mode, cells whose current output is marginal in the unprogrammed state will be detected as faulty, even though those same cells would correctly be read as unprogrammed.
Inventors:
GORUTEIE JANNMARII
SHIRUESUTORU DEYU FUERON JERAARU
GASUTARUDEI ROBERUTO
SHIRUESUTORU DEYU FUERON JERAARU
GASUTARUDEI ROBERUTO
Application Number:
JP51359291A
Publication Date:
December 20, 1999
Filing Date:
August 06, 1991
Export Citation:
Assignee:
ESU TEE MIKUROEREKUTORONIKUSU SA
International Classes:
G01R31/28; G11C16/06; G11C16/28; G11C29/00; G11C17/00; G11C29/12; G11C29/24; G11C29/50; (IPC1-7): G11C29/00; G01R31/28; G11C16/06
Domestic Patent References:
| JP63293800A | ||||
| JP62222498A | ||||
| JP1165095A | ||||
| JP5853090A |
Other References:
【文献】R.GASTALDI et al.,“A 1-Mbit CMOS EPROM with enhanced verification”,
Attorney, Agent or Firm:
Takashi Koshiba