Title:
【発明の名称】コンピュータシステムの節電制御装置
Document Type and Number:
Japanese Patent JP3058986
Kind Code:
B2
Abstract:
A power saving control system for a computer system including a CPU, is provided with a mode selecting circuit for selectively operating the CPU in a first mode with relatively high performance and high power consumption and a second mode with relatively low performance and low power consumption, a repeated access detecting circuit for monitoring addresses accessed by the CPU over a given period in order to detect a predetermined operational state of the CPU, in which only specific address group is repeatedly accessed, a control circuit associated with the first means for normally operating the first means in the first mode and responsive to the second means detecting the predetermined operational state, for operating the first means in the second mode as long as the predetermined operational state is maintained, and a state display for generating an indication perceptible by an operator of the computer system indicating current operational mode of the CPU.
Inventors:
Osamu Ikeda
Application Number:
JP8080792A
Publication Date:
July 04, 2000
Filing Date:
April 02, 1992
Export Citation:
Assignee:
Dia Semicon Systems Co., Ltd.
International Classes:
G06F1/04; G06F1/32; G06F11/32; (IPC1-7): G06F1/32; G06F1/04
Domestic Patent References:
| JP4195316A | ||||
| JP3266015A | ||||
| JP477810A | ||||
| JP519917A | ||||
| JP695303B2 |
Attorney, Agent or Firm:
Kensuke Isshiki (2 outside)