Title:
【発明の名称】基板バイアス回路
Document Type and Number:
Japanese Patent JP3135859
Kind Code:
B2
Abstract:
A substrate biasing circuit includes a logical threshold potential output circuit including transistors formed on a semiconductor substrate and generating a logical threshold potential. A potential compare control circuit compares the logical threshold potential with a reference potential and generating a control potential based on a comparison result. A substrate bias generating circuit generates, as long as the control potential indicates that the logical threshold potential is not equal to the reference potential, a substrate potential applied to the semiconductor substrate so that the logical threshold potential is equal to the reference potential, and stops operating after the logical threshold potential becomes equal to the reference potential. A switch circuit breaks a pass-through current path formed in the logical threshold potential output circuit when the control potential indicates that the logical threshold potential becomes equal to the reference potential.
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Inventors:
Yasuyuki Shindo
Hirofumi Watanabe
Hirofumi Watanabe
Application Number:
JP9372197A
Publication Date:
February 19, 2001
Filing Date:
April 11, 1997
Export Citation:
Assignee:
株式会社リコー
International Classes:
G11C11/413; G05F3/20; G11C11/408; H01L21/822; H01L27/04; H02M3/07; H03K19/094; (IPC1-7): G11C11/408; G11C11/413; H03K19/094
Domestic Patent References:
| JP6139779A | ||||
| JP4297119A |
Attorney, Agent or Firm:
Hiroshi Torii
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