Title:
【発明の名称】ICテスタ及びICの試験方法
Document Type and Number:
Japanese Patent JP3269085
Kind Code:
B2
Abstract:
PURPOSE:To carry out an IC test in parallel even when a test timing condition is different from each other by reading a pattern signal in order from a memory part correspondent to a plurality of timing signals, and by inputting it to a plurality of formatters. CONSTITUTION:A pattern SP based on the set frequency of a timing generator 2a is generated by a pattern generator 1, and as it is supplied to formatters 5a-5d, it is stored in memory parts 3a, 3b at a timing sta set by the timing generator 2a. The pattern in the memory parts 3a, 3b is read at timings stb, stc of the frequency set by timing generators 2b, 2c, and is applied to IC memories to be tested 7a-7d as test patterns STP1-STP4 through the formatters 5a-5d. Output signals SO1-SO4 of each memory 7a-7d are compared with estimated patterns SE1, SEa, SEb generated from the generator 1 as well as the memory parts 3a, 3b by comparators 8a-8d, and are judged thereby.
Inventors:
Atsushi Nigorikawa
Application Number:
JP828191A
Publication Date:
March 25, 2002
Filing Date:
January 28, 1991
Export Citation:
Assignee:
NEC
International Classes:
G01R31/28; H01L21/66; G01R31/26; (IPC1-7): G01R31/28; G01R31/26; H01L21/66
Domestic Patent References:
| JP58135972A | ||||
| JP59773A | ||||
| JP60120269A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)