Title:
【発明の名称】論理レベル制御回路
Document Type and Number:
Japanese Patent JP3280405
Kind Code:
B2
Abstract:
A logic level control circuit prevents impact ionization in a CMOS integrated circuit. The substrate bias voltage of the CMOS integrated circuit is detected by the control circuit and a control signal is provided in response to the detected bias voltage. The bias voltage can be zero volts or negative five volts. If the bias voltage is zero volts, the control signal is a logic level one. If the bias voltage is negative five volts, the control signal is a logic level zero. The control signal is applied to the gate of at least one other controlled device on the integrated circuit for turning that controlled device on and off. The controlled device coupled to a further CMOS device and turning the controlled device on and off prevents impact ionization by allowing the controlled device to alternately divide a voltage level with the further CMOS device or be effectively removed from the circuit.
Inventors:
Michael kees mys
Application Number:
JP30089091A
Publication Date:
May 13, 2002
Filing Date:
November 16, 1991
Export Citation:
Assignee:
National Semiconductor Corporation
International Classes:
G11C11/417; G11C11/413; H01L21/822; H01L27/04; H03K17/081; H03K17/10; H03K17/16; H03K17/687; (IPC1-7): H03K17/16; H01L21/822; H01L27/04; H03K17/687
Domestic Patent References:
| JP1149448A | ||||
| JP373565A | ||||
| JP6171658A | ||||
| JP5391649A | ||||
| JP63307771A | ||||
| JP62501043A |
Attorney, Agent or Firm:
Masaaki Kobashi