Title:
【発明の名称】キャッシュSDRAMデバイス
Document Type and Number:
Japanese Patent JP3335298
Kind Code:
B2
Abstract:
A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.
Inventors:
Jim Lewis Rogers
Stephen william tomashot
Stephen william tomashot
Application Number:
JP28077797A
Publication Date:
October 15, 2002
Filing Date:
October 14, 1997
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G11C11/407; G06F12/08; G11C11/401; G11C11/409; (IPC1-7): G11C11/407; G11C11/401
Domestic Patent References:
| JP785656A | ||||
| JP6381692A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)