Title:
【発明の名称】スキャンパス用フリップフロップ回路及びスキャンパステストシステム
Document Type and Number:
Japanese Patent JP3357821
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a flip-flop circuit by which the facilitation of a test by the automation tool of a circuit can be designed by a method wherein the flip- flop circuit is operated in synchronization with the fall edge of a clock signal so as to correspond to a gated clock system in an ordinary operation mode and the flip-flop circuit is operated in synchronization with the rise edge of the clock signal in a test operation mode. SOLUTION: In an ordinary operation mode, a flip-flop circuit which receives a gated clock signal so as to be operated fetches input data in synchronization with a clock signal in a potential change direction, on the other side, opposite to the potential change direction, on one side, of the clock signal, the data is output from a data output terminal, and inverted data is output from an inverted-data output terminal. In a test system mode, data is fetched in synchronization with the clock signal in the potential change direction on one side, and the data is output from a scan-data output terminal. In a test scan mode, input scan data is fetched in synchronization with the clock signal in the potential change direction on one side, and the data is output from the scan-data output terminal.
Inventors:
Ryoji Kusano
Application Number:
JP25565597A
Publication Date:
December 16, 2002
Filing Date:
September 19, 1997
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F11/22; H03K3/037; H03K19/00; G01R31/28; (IPC1-7): G01R31/28; G06F11/22; H03K3/037; H03K19/00
Domestic Patent References:
| JP6089120A | ||||
| JP5180911A | ||||
| JP8105941A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)