Title:
【発明の名称】コンピュータシステム
Document Type and Number:
Japanese Patent JP3382087
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To directly access a memory device without interposing any cache memory. SOLUTION: A processor 101 outputs an instruction for writing the high-order 12 bits of an address into a control register 11-1 to a bus access control part 11. The bus access control part 11 writes the high-order 12 bits of the address into the control register 11-1. The processor 1-1 outputs an instruction for write into any specified area W inside a non-caching space to the bus access control part 11. The bus access control part 11 discriminates access to the area W and generates the address of a memory device 2 from the address of the area W outputted from the control register 11-1 and the processor 1-1. Then, a control signal for write into the memory device 2 is generated and these control signal, address and data are transferred to a bus 4.
Inventors:
Takashi Matsuse
Shigeru Tachizawa
Isao Kato
Naokazu Ito
Shigeru Tachizawa
Isao Kato
Naokazu Ito
Application Number:
JP13234696A
Publication Date:
March 04, 2003
Filing Date:
May 27, 1996
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G06F12/08; G06F12/00; (IPC1-7): G06F12/08; G06F12/00
Domestic Patent References:
| JP5225058A | ||||
| JP462648A | ||||
| JP4326437A |
Attorney, Agent or Firm:
Yasunari Kakimoto