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Title:
コンピュータにおけるバイト順番スイッチング方法及び装置
Document Type and Number:
Japanese Patent JP3556955
Kind Code:
B2
Abstract:
A method and apparatus which enables a given computer to run programs using either a big endian or little endian architecture is disclosed. The method uses the fact that exclusive-ORing the lower two bits of a byte address in one architecture with binary 3 converts that byte address to the equivalent byte address in the other architecture. The method is implemented in software in a preferred embodiment, but a hardware implementation is also disclosed.

Inventors:
Larry Bee. Weber
R.A. Cillian
Mark Eye. Himelstein
Application Number:
JP19784991A
Publication Date:
August 25, 2004
Filing Date:
August 07, 1991
Export Citation:
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Assignee:
MIPS Technologies, Inc.
International Classes:
G06F9/06; G06F5/00; G06F7/76; G06F9/34; G06F9/44; G06F9/455; G06F12/04; (IPC1-7): G06F9/44; G06F5/00; G06F9/455; G06F12/04
Domestic Patent References:
JP60128543A
JP61160144A
JP6263340A
JP60129868A
JP62154102A
JP63211019A
JP63217416A
JP2113381A
JP63208146A
JP62184530A
JP454551A
Other References:
James, D.V.,"Multiplexed buses: the endian wars continue",IEEE Micro,1990年 6月,Vol.10, No.3,pp.9-21
Kirrmann, H.,"Data Format and Bus Compatibility in Multiprocessors",IEEE Micro,1983年,Vol.3, No.4,pp.32-47,JST資料番号:H0837A
Cohen, D.,"On holy wars and a plea for peace",Computer,1981年,Vol.14, No.10,pp.48-54,JST資料番号:B0794A
Attorney, Agent or Firm:
Masaaki Kobashi