Title:
半導体装置用パッケージ
Document Type and Number:
Japanese Patent JP3577421
Kind Code:
B2
Abstract:
A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers; wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers.
Inventors:
Takahiro Iijima
Akio Rokukawa
Akio Rokukawa
Application Number:
JP1599599A
Publication Date:
October 13, 2004
Filing Date:
January 25, 1999
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H01L23/498; H01L23/12; H05K1/11; H05K3/46; (IPC1-7): H01L23/12
Domestic Patent References:
| JP8264957A | ||||
| JP10270850A | ||||
| JP10032283A | ||||
| JP7106464A | ||||
| JP2000100988A |
Attorney, Agent or Firm:
Takao Watanuki
Horimai Kazuharu
Horimai Kazuharu