Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP3597403
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a test function capable of testing process operations by use of a various-purpose logic tester when testing the semiconductor integrated circuit device in a semiconductor integrated circuit device for processing a data signal while inputting a data signal in response to a high-speed clock. SOLUTION: An n-bit data signal in response to a high-speed clock of a frequency f to be input from the outside is made N times by a data signal conversion part 2, to convert it into an N×n-bit data signal, and also a clock of frequency f to be input from externally is divided 1/N times by a divider 3. The such-converted data signal and clock are performed data process by a main circuit 4, whereby when operations of the main circuit 4 are tested by a tester, a various-purpose logic tester operating in synchronism with the clock of a frequency f/N is directly connected to the main circuit 4, thereby inspecting it.
Inventors:
Yasunori Kawamura
Application Number:
JP1449199A
Publication Date:
December 08, 2004
Filing Date:
January 22, 1999
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
G01R31/28; H01L21/822; H01L27/04; G06F11/22; (IPC1-7): G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP9269356A | ||||
| JP2292855A | ||||
| JP4087362A | ||||
| JP9197009A | ||||
| JP11174120A | ||||
| JP697283A | ||||
| JP5264667A | ||||
| JP4220576A | ||||
| JP2134842A | ||||
| JP63198366A |
Attorney, Agent or Firm:
Shizuo Sano