Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP3829088
Kind Code:
B2
Abstract:
A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.
Inventors:
Mitsuhiro Noguchi
Akira Goda
Yasuhiko Matsunaga
Akira Goda
Yasuhiko Matsunaga
Application Number:
JP2001383554A
Publication Date:
October 04, 2006
Filing Date:
December 17, 2001
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C16/04; G11C16/06; G11C16/26; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2000285692A |
Attorney, Agent or Firm:
Masaru Itami