Title:
受信機
Document Type and Number:
Japanese Patent JP4016945
Kind Code:
B2
Abstract:
Receiver comprising an RF front end circuit for a selection and conversion of an RF input signal into a pair of quadrature IF (intermediate frequency) signals being supplied through in-phase and phase quadrature signal paths to signal inputs of quadrature phase detection means included in a (PLL) phase locked loop, an output of said quadrature phase detection means being coupled through a loop filter to a control input of a quadrature IF oscillator supplying a pair of quadrature IF oscillator signals to carrier inputs of said quadrature phase detection means. To suppress amplitude and phase mismatch deteriorating proper mirror cancellation said quadrature phase detection means is coupled to amplitude and phase error detection means for a detection of amplitude and phase errors in the output signal of said quadrature phase detection means and a quadrature frequency doubler is coupled between the quadrature local oscillator and carrier inputs of said amplitude and phase error detection means to supply respectively thereto in-phase and phase quadrature error detection carrier signals at twice the IF carrier frequency of said pair of quadrature IF signals, said amplitude and phase error detection means respectively providing amplitude and phase error signals through first and second low-pass filters to an amplitude correction circuit and a phase correction circuit preceding at least one of the inputs of said quadrature phase detection means for a negative feedback of said amplitude and phase errors.
Inventors:
Kasperkovitz Wolf Dietrich Georg
Application Number:
JP2003527878A
Publication Date:
December 05, 2007
Filing Date:
September 01, 2002
Export Citation:
Assignee:
Semiconductor Ideas To The Market (ITOM) BV
International Classes:
H04B1/26; H04L27/00; H03D3/00; H03D3/24; H03D5/00
Domestic Patent References:
| JP59186431A |
Attorney, Agent or Firm:
Masao Sawada