Title:
ヘッドIC回路及び記録装置
Document Type and Number:
Japanese Patent JP4019333
Kind Code:
B2
Abstract:
A register address and control data which were serially transferred from an outside by a serial interface unit are received, the received head address is stored into a head address control register, and a head selection signal corresponding to the head address is outputted. When the setting of an automatic head switching mode is received from the outside, an automatic head switching control unit automatically switches the contents of the head address control register and sequentially outputs the head selection signals to a plurality of heads synchronously with a write gate signal (WRGT signal) E8 to instruct the writing operation from the outside.
Inventors:
Isamu Tomita
Application Number:
JP3077498A
Publication Date:
December 12, 2007
Filing Date:
February 13, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11B5/09; G11B5/012; G11B20/10; G11B33/12
Domestic Patent References:
| JP9161208A | ||||
| JP8235801A | ||||
| JP2254685A | ||||
| JP8293174A |
Attorney, Agent or Firm:
Susumu Takeuchi
Saichiro Miyauchi
Saichiro Miyauchi