Title:
効率的なパラレルステージ電力アンプ
Document Type and Number:
Japanese Patent JP4024867
Kind Code:
B2
Abstract:
An amplifier circuit for providing an amplified signal in response to an input signal. The amplifier circuit includes an input network for applying the input signal to a selected at least one of a plurality of amplifier stages. An output network is provided for coupling the amplified signal from the selected at least one amplifier stage. The appropriate amplifier stage is selected by a control circuit in response to a desired power value of the amplified signal. By selectively activating only the amplifier stage(s) that are necessary to provide the desired level of output power, increased DC efficiency can be accomplished in applications that require an amplifier which operates linearly over a wide dynamic range.
Inventors:
Cevik, John F
Camarillo, Richard Jay
Camarillo, Richard Jay
Application Number:
JP52679198A
Publication Date:
December 19, 2007
Filing Date:
December 05, 1997
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03F99/00; H03F1/02; H03G3/00; H03F1/32; H03F3/60; H03F3/68; H03F3/72; H03G3/02; H03G3/30; H04B1/04; H04B7/26
Domestic Patent References:
| JP5029859A | ||||
| JP7066841A | ||||
| JP4054006A |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Ryo Hashimoto
Tetsuya Kazama
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Ryo Hashimoto
Tetsuya Kazama