To realize a signal inversion processor with a required minimum memory capacity.

A vertical counter 71 is counted up one by one during a display section of an OSD signal at each time of detection of a horizontal synchronizing signal and is fixed to a prescribed value during a section other than the display section. A horizontal counter 72 is counted up one by one during the display section of the OSD signal at each time of detection of a system clock in the case of an even counted number of the vertical counter 71 and is counted down one by one in the case of an odd counted number of the vertical counter 71, and is fixed to a prescribed value during a section other than the display section. A memory controller 61 connects an inversion of the LSB of the horizontal counter 72 to the write enable terminal of a memory 62 when the counted number of the vertical counter 71 is even, and connects the LSB of the horizontal counter 72 when the counted number of the vertical counter 71 is odd, and connects upper bits other than the LSB of the horizontal counter 72 to the address terminal of the memory 62. Thus read and write are performed for one address in order. The signal inversion processor is applicable for a liquid crystal display panel.

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