Title:
遅延同期ループ
Document Type and Number:
Japanese Patent JP4043024
Kind Code:
B2
Abstract:
A delay locked loop circuit includes a delay unit for receiving an input clock signal, generating an output clock signal whose phase lags that of the input clock signal, and generating multiple delay signals having differently delayed phases in response to the input clock signal; a harmonic lock preventing unit for receiving the input clock signal and the multiple delay signals, outputting a 1signal and a 2signal, comparing the phases of the input clock signal and the multiple delay signals, and generating the 1signal or the 2signal depending on the comparison result; an electric charge pump for receiving the 1signal and the 2signal, generating a phase control signal, and making the voltage of the phase control signal higher or lower than a pre-defined voltage in response to the 1signal and the 2signal; a filter for eliminating AC included in the phase control signal and transmitting the filtered signal to the delay unit; and start-up circuits for feeding a 1voltage to the electric charge pump in the initial state before the output clock signal is generated and making the electric charge pump provide a 2voltage to the delay unit; wherein the delay unit provides a delay locked circuit that adjusts the phases of the output clock signal and the multiple delay signals in response to the phase control voltage.
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Inventors:
High Life Dragon
Application Number:
JP2002287106A
Publication Date:
February 06, 2008
Filing Date:
September 30, 2002
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06F1/12; H03L7/081; G06F1/10; G11C11/407; G11C11/4076; H03K5/14; H03L7/08; H03L7/089; H03L7/10; H03L7/087
Domestic Patent References:
| JP2000341100A | ||||
| JP6164377A |
Attorney, Agent or Firm:
Makoto Hagiwara