Title:
マルチスレッド・プロセッサにおいて処理する命令スレッドを選択するための方法および装置
Document Type and Number:
Japanese Patent JP4086808
Kind Code:
B2
Abstract:
The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.
Inventors:
Ronald N Cala
Min Michelle Kew Fam
Balaram Singhaloy
John W. Ward III
Min Michelle Kew Fam
Balaram Singhaloy
John W. Ward III
Application Number:
JP2004119571A
Publication Date:
May 14, 2008
Filing Date:
April 14, 2004
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06F9/46; G06F7/38; G06F9/38; G06F15/00
Domestic Patent References:
| JP9282184A | ||||
| JP10124316A | ||||
| JP2000020323A | ||||
| JP2001306323A | ||||
| JP2002268878A |
Foreign References:
| WO2000067113A1 | ||||
| WO2002067116A2 | ||||
| US6073159 | ||||
| US6076157 | ||||
| US6212544 | ||||
| US6981261 | ||||
| US20010056456 | ||||
| US20020103990 |
Other References:
SNAVELY, A., et al.,Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor,SIGMETRICS Conf. Measurement and Modeling of Comput. Syst.,2002年 6月,pp. 66 - 76
内山真郷外,リアルタイム処理用マルチスレッドプロセッサの設計と実装,電子情報通信学会技術研究報告,2000年 3月22日,第99巻,第725号,p.29-36
内山真郷外,リアルタイム処理用マルチスレッドプロセッサの設計と実装,電子情報通信学会技術研究報告,2000年 3月22日,第99巻,第725号,p.29-36
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno