Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4113338
Kind Code:
B2
Abstract:
A timing signal generator receives a plurality of control signals in synchronization with a clock signal, and generates a timing signal according to a combination of the control signals. A delay circuit delays an input signal received asynchronously to the clock signal by a predetermined time. A receiving circuit receives the input signal which is delayed by the delay circuit, in synchronization not with the clock signal but with the timing signal. Namely, the receiving circuit operates asynchronously to the clock signal, and receives only necessary input signals for the semiconductor integrated circuit. This lowers operation frequency of the receiving circuit, thereby reducing power consumption. The number of the circuits to be operated in synchronization with the clock signal can be reduced, by which reduces standby current. An increase in the standby current is gradual even when frequency of the clock signal goes high.
Inventors:
Yoshimasa Yanashita
Application Number:
JP2001110851A
Publication Date:
July 09, 2008
Filing Date:
April 10, 2001
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/407; G11C7/10; G11C7/22; G11C8/06; G11C8/18; G11C11/4076; G11C11/4093; H03K5/00
Domestic Patent References:
| JP9198875A | ||||
| JP6096578A | ||||
| JP11016348A | ||||
| JP9198872A |
Attorney, Agent or Firm:
Furuya Fumio