Title:
多層半導体チップ・パッケージ、コネクタ及び半導体チップ・パッケージを製造する方法
Document Type and Number:
Japanese Patent JP4140907
Kind Code:
B2
Abstract:
A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.
Inventors:
Patrick H. Buffett
Charles S. Ju
John Dee Garrett
Luis El Che
Brian jay shoe
Charles S. Ju
John Dee Garrett
Luis El Che
Brian jay shoe
Application Number:
JP2004237572A
Publication Date:
August 27, 2008
Filing Date:
August 17, 2004
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L23/12; H01L23/64
Domestic Patent References:
| JP5041463A | ||||
| JP2003133472A | ||||
| JP2001203292A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno