Title:
半導体集積回路装置の製造方法
Document Type and Number:
Japanese Patent JP4142664
Kind Code:
B2
Abstract:
To keep oxide contamination on a substrate surface prior to ion implantation at a low level, after a polymetal gate has been processed.
Gate electrodes 7A, 7B, and 7C that include a tungsten (W) film are formed, followed by being subjected to re-oxidation a treatment on condition that the tungsten film is not practically oxidized. In succession, after the main surface of a substrate 1 has been wet-cleaned, by using a neutral or mildly alkaline water solution that does not practically contain hydrogen peroxide, impurities are ion-implanted to the main surface of the substrate 1.
COPYRIGHT: (C)2005,JPO&NCIPI
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Inventors:
Naoki Yamamoto
Hiroyuki Uchiyama
Norio Suzuki
Eisuke Nishitani
Shinichiro Kimura
Kazuyuki Parkzawa
Hiroyuki Uchiyama
Norio Suzuki
Eisuke Nishitani
Shinichiro Kimura
Kazuyuki Parkzawa
Application Number:
JP2005104585A
Publication Date:
September 03, 2008
Filing Date:
March 31, 2005
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/28; H01L21/3205; H01L21/8238; H01L21/8242; H01L21/8247; H01L23/52; H01L27/092; H01L27/108; H01L27/115; H01L29/423; H01L29/49; H01L29/788; H01L29/792
Domestic Patent References:
JP9266178A | ||||
JP10335652A | ||||
JP10223900A | ||||
JP2000331978A | ||||
JP11330468A | ||||
JP11204456A | ||||
JP7094731A | ||||
JP3147328A | ||||
JP2000349285A |
Attorney, Agent or Firm:
Yamato Tsutsui